I stumbled upon a LinkedIn post by Michaela Eichinger (from Quantum Machines), who asked a great and relevant question about the meaning of a QPU, summarised below:
Quantum chip connected to a circuit board - credits: QUtechThe Quantum Processing Unit (QPU) is not just the bare chip: In classical semiconductors, CPUs are more than just bare silicon die post-tape-out. Without the packaging, clock distribution, memory hierarchies, and microcode, that die is just highly engineered sand.
The exact same systems-engineering rigor holds for the QPU. On its own, the quantum chip does nothing. It needs the right packaging and environment (like a dilution fridge or vacuum chamber), as well as the control circuitry and infrastructure to actually execute logic gates.
Terminology Link to heading
Among all the comments on the question, Olivier Ezratty’s was especially practical. He suggested defining two key terms to clarify things: “quantum computer” and “quantum computing system.”
Quantum computer: runs a predefined quantum circuit, usually multiple times, and provides useful results. So it includes compilation, optimization, QEC/FTQC implementation if any, all classical system drive (electronics, photonics), mid-circuit measurements, classical optimizer (for NISQ variational circuits), and post-processing. And all enabling techs, including cryogenics.
Quantum computing system: solves a user problem using a quantum computer. It should include all classical resources involved in the quantum circuit generation, up to some HPC if required. And the used quantum computer.
The diagram on the right represents those two definitions.
System Perspective: [ QPU || GPU ] Link to heading
The interesting part is the Quantum computing system. I like to draw a parallel between the QPU and GPU stack, as shown in the following diagram:
From a system perspective, a QPU is not so different from a GPU. There are analogies between the different layers of the QPU and GPU stacks.
It is also helpful to identify which parts operate on the quantum hardware and which logical components run on the classical computer, even if both are part of the quantum computer.
Olivier Erzaty gave helpful feedback on the original diagram I posted on LinkedIn:
Interconnect: There are at least two interconnects. The quantum interconnect carries entangled quantum entities. The real-time classical interconnect, called the real-time interconnect (RTI) in NVQLink terms, is another. There is also a standard classical network connecting the CPUs, which is not shown in this diagram.
Calibration: Ideally, calibration should be real time, but in most cases it is not yet. Today, there are two types: real-time calibration, which runs within the quantum hardware using on-board NPUs and readout or syndrome data, and slower calibration, which runs on the CPU or GPU using advanced vLLM models like Ising. These two approaches may eventually merge, but that could take a few years.
Acceleration: The first diagram used the term “quantum hardware acceleration” to highlight that quantum circuits can also run on GPU-accelerated simulators, even without a QPU. However, as Olivier noted, some quantum fields like QML use quantum solutions to improve results, but not necessarily for speed. To avoid confusion, the parts specific to quantum hardware (sequencer, controllers, pulsar, cryo, and quantum chips) are called “Quantum Hardware.”
System Hierarchy Link to heading
This leads to the following hierarchy, similar to what Olivier proposed:
- Quantum System: A heterogeneous & hybrid system that operates GPUs, CPUs, QPUs together.
- Quantum Computer: A system that execute quantum circuits and generate probabilistic readouts.
- Quantum Hardware: The physical part where the QPU is located, along with the cryo and PPU.
Here are a few points to note:
xPUs: I mentioned “GPUs, CPUs, and QPUs,” but I could have used “xPU” as a general term for any processing unit, since the system might also use TPUs and NPUs.
PPUs: The PPU stands for “Pulse Processing Unit”. It is the component the firmware is running on, responsible for control and readout pulsars’, (mid-circuit) sequencing, QEC, and RTI networking.
GPU vs PPU: Running kernels on the GPU or PPU involves a tradeoff between the cost of moving information and computing power, especially when PPUs are placed inside the cryostat.
Conclusion Link to heading
This short memo helped me clarify the different components in a quantum computing system that operates QPUs. I used the GPU analogy on purpose to make it easier to understand the components involved with a QPU.
Of course, this is a simplified view, and I left out many details on purpose. I’ll cover those in future memos. In the meantime, if you’re interested, check out CudaQ from Nvidia, which already tackles many of the design challenges shown in the top part of this diagram.
I’d also like to thank Oliver Erzaty for his feedback and Michaela Eichinger for her always insightful questions and posts.
References:
- NVQLink: Real-time accelerated computing for every quantum processor
- CudaQ: NVIDIA’s open platform for quantum computing and the foundation for accelerated quantum supercomputing
- PPU: Real-Time Quantum Control at the Pulse Level
- NVIDIA Ising
For reference, this is the initial diagram posted on LinkedIn:
DrawIO diagrams used in this memo:
